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1、libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;----Uncommentthefollowinglibrarydeclarationifinstantiating----anyXilinxprimitivesinthiscode.--libraryUNISIM;--useUNISIM.VComponents.all;entitycounterisPort(clk:i
2、nstd_logic;resetn:instd_logic;dout:outstd_logic_vector(7downto0);lcd_en:outstd_logic;lcd_rs:outstd_logic;lcd_rw:outstd_logic);endcounter;architectureBehavioralofcounteriscomponentcounter60isPort(clk:instd_logic;resetn:instd_logic;dout:outstd_logic_vector(7dow
3、nto0));endcomponent;componentdecoderisPort(din:instd_logic_vector(3downto0);dout:outstd_logic_vector(8downto0));endcomponent;componentlcd_interfaceisport(clk:instd_logic;resetn:instd_logic;dout_s10:instd_logic_vector(8downto0);dout_s1:instd_logic_vector(8down
4、to0);lcd_data:outstd_logic_vector(7downto0);lcd_en:outstd_logic;lcd_rs:outstd_logic;lcd_rw:outstd_logic);endcomponent;signalddout_s10:std_logic_vector(8downto0);signalddout_s1:std_logic_vector(8downto0);signalddout:std_logic_vector(7downto0);beginu1:counter60
5、portmap(clk,resetn,ddout);u2:decoderportmap(ddout(7downto4),ddout_s10);u3:decoderportmap(ddout(3downto0),ddout_s1);u4:lcd_interfaceportmap(clk,resetn,ddout_s10,ddout_s1,dout,lcd_en,lcd_rs,lcd_rw);endBehavioral;-------------------------------------------------
6、---------------------------------Company:--Engineer:----CreateDate:13:36:1003/30/06--DesignName:--ModuleName:count60-Behavioral--ProjectName:--TargetDevice:--Toolversions:--Description:----Dependencies:----Revision:--Revision0.01-FileCreated--AdditionalCommen
7、ts:----------------------------------------------------------------------------------libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;entitycounter60isPort(clk:instd_logic;resetn:instd_logic;dout:outstd_logic_v
8、ector(7downto0));endcounter60;architectureBehavioralofcounter60issignalcount:std_logic_vector(7downto0);signalcount_div:std_logic_vector(25downto0);begindout<=count;process(clk)beginif(cl
