an edge-endpoint-based configurable hardware architecture for vlsi cad layout design rule c

an edge-endpoint-based configurable hardware architecture for vlsi cad layout design rule c

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時間:2019-03-06

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1、AnEdge-Endpoint-BasedConfigurableHardwareArchitectureforVLSICADLayoutDesignRuleCheckingZhenLuo,MargaretMartonosiandPranavAsharPrincetonUniversityandNECCCRL{zhenluo,mrm}@ee.princeton.edu,ashar@ccrl.nj.nec.comAbstractsetofchanges.PasthardwareDRCapproachesavoidedthisredesigncy

2、clebyacceleratingonlythebasicDesignrulechecking(DRC)isanimportantstepinVLSIdesignprimitivesofDRC,notthespecificrulechecks.TheinwhichthewidthsandspacingsofdesignfeaturesinaVLSIdrawbacktosuchapproachesisthattheyaccelerateonlyacircuitlayoutarecheckedagainstthedesignrulesofapor

3、tionoftheDRCanddonotadequatelyaddressthetrueparticularfabricationprocess.Inthepast,someeffortstobuildcomputebottlenecks.hardwareacceleratorsforDRChavebeenproposed,buttheseeffortswerehobbledbythefactthatitisoftenimpracticaltoOurproposalnotesthatwhiledesignrulesdochangeoverbu

4、ildadifferentrule-checkingASICeachtimedesignrulesorfabricationprocesseschange.timeandvarybetweenfabricationlines,theirfundamentalformremainssimilar.Thus,ourgoalistodesignaInthispaper,weproposeaconfigurablehardwareapproachtogeneral-purposeskeletonforDRCthatappliestonearlyDRC

5、.Becausetherule-checkingisbuiltinconfigurableallfabricationdesignrules,andthenalsototailorthehardware,itcangarnerimpressivespeedupsoversoftwarerule-checkinghardwareforaparticularfabricationapproaches,whileretainingtheflexibilityneededtoeasilyprocess.Tailoringtherule-checkst

6、oanindividualchangetherulecheckerasrulesorprocesseschange.Ourworkprocessallowsformuchbetterspeedupsandtakesproposesanedge-endpoints-basedmethodforperformingadvantageoftheinherentflexibilityofconfigurableManhattangeometrychecking;thisapproachisparticularlyhardware.Atthesamet

7、ime,thereconfigurationsarewell-suitedtotheconstraintsofconfigurablehardware.Althoughdesignrulesdochangeovertime,theirintrinsiclikelytobeinfrequentenough(every6-12months)thatsimilarityallowsustoproposeageneralscalablearchitecturetheFPGAreconfigurationtimeshaveessentiallynofo

8、rDRC.Wethendemonstrateourapproachbyapplyingthisimpactonperformance.architecturetoa

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