數(shù)據(jù)采集及監(jiān)控系統(tǒng)

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1、數(shù)據(jù)采集及監(jiān)控系統(tǒng)鄭州輕院輕工職業(yè)學(xué)院專科畢業(yè)設(shè)計(jì)（論文）題目數(shù)據(jù)采集及監(jiān)控系統(tǒng)學(xué)生姓名王冠峰專業(yè)班級07電子信息（4）班學(xué)號07010301120院（系）鄭州輕院輕工職業(yè)學(xué)院機(jī)電工程系指導(dǎo)教師(職稱)張少鋒（助教）完成時間2010年4月15日16數(shù)據(jù)采集及監(jiān)控系統(tǒng)數(shù)據(jù)采集及監(jiān)控系統(tǒng)摘要本文采用FPGA器件AC0809芯片控制A/D轉(zhuǎn)換進(jìn)行采樣控制，整個設(shè)計(jì)用VHDL語言描述，在QuartusⅡ平臺下執(zhí)行軟件編程實(shí)現(xiàn)正確的A/D轉(zhuǎn)換的工作時序控制流程，并將采樣數(shù)據(jù)從二進(jìn)制轉(zhuǎn)化成BCD碼。本設(shè)計(jì)可用于高速使用領(lǐng)域和實(shí)時

2、監(jiān)控方面。在以往的A/D器件采樣控制設(shè)計(jì)中，多數(shù)是以單片機(jī)或CPU為控制核心，雖然編程基本，控制靈活，但缺點(diǎn)是控制周期長，速度慢。單片機(jī)的速度極大的限定了A/D高速性能的運(yùn)用，而FPGA的時鐘頻率可高達(dá)100MHz以上。本設(shè)計(jì)以高集成度的芯片為核心，執(zhí)行時序控制、碼制變換。具有開發(fā)周期短，靈活性強(qiáng)，通用能力好，易于開發(fā)、擴(kuò)展等優(yōu)點(diǎn)。既降低了設(shè)計(jì)難度，又加快了產(chǎn)品的開發(fā)周期。本系統(tǒng)主要由三大部分組成：數(shù)據(jù)輸入單元，數(shù)據(jù)處理單元，數(shù)據(jù)輸出單元。本設(shè)計(jì)主要實(shí)現(xiàn)以下幾個功能：對ADC0809的八路通道的數(shù)據(jù)進(jìn)行循環(huán)檢測，當(dāng)檢

3、測到任何一路的值大于預(yù)設(shè)值的時候就進(jìn)行報(bào)警，并顯示出所超出規(guī)定值的通道數(shù)。如無任何通道的輸出值超出預(yù)設(shè)值時，就進(jìn)行通道0~通道7的循環(huán)檢測。關(guān)鍵詞：FPGA；A/D轉(zhuǎn)換；VHDL；采樣控制；16數(shù)據(jù)采集及監(jiān)控系統(tǒng)THEDATACOLLAGEANDSUPERVISESANDCONTROLSSYSTEMABSTRACTThisliterarygraceisusedFPGAthesparepartAC0809chipcontrolA

4、theDconversioncarryonasamplecontrol,thewholed

5、esignisusedaVHDLlanguagedescriptionandcarryoutasoftwareplaitundertheterraceofQuartusⅡthedistancecarryoutcorrectA

6、Dconversionofworkcycletimecontrolprocess,andconvertto°fromthebinarysystemasampledataBCDcode.Thisdesigncanbeusedforahighspeedusagerealmandsolidsuperv

7、iseandcontrolaspect.IntheformerA

8、theDsparepartsamplecontroldesignin,majorityistakethesinglesliceofmachineorCPUastocontrolcore,althoughweavingadistanceisbasicandcontrolvivid,theweaknessistocontrolaperiodlong,thespeedisslow.Thespeedofthesinglesliceofmachinebigges

9、tlimitedA

10、theusageoftheDhigh-speedfunction,buttheFPGAclockfrequencycanbeuptoa100MHzsabove.Thisdesigntakesthechipofhighintegrationdegreeascoreandcarryoutcycletimecontrol,codesystemtransformation.Havingtodevelopaperiodisshort,thevividisstrong,ingeneraluseabilityg

11、ood,beeasytoadevelopmentandexpandetc.advantage.Sinceloweredadesigndifficulty,inadditionquickthedevelopmentperiodofproduct.Thissystemmainlyconstitutesto°fromthreebigparts:Thedatainputsunit,thedatahandlesunit,andthedataoutputsunit.Thisdesignismaintocarryoutfollow

12、ingfewfunctionses:CarryonacirculationexaminationtothedataofeightroadpassagesofADC0809,betheexaminationarriveanyallthewayofthevalueisbiggerthantopreparetoestablishavalueoftim