資源描述：
《51單片機(jī)與fpga進(jìn)行串行通信》由會(huì)員上傳分享，免費(fèi)在線閱讀，更多相關(guān)內(nèi)容在教育資源-天天文庫(kù)。
1、51單片機(jī)與fpga進(jìn)行串行通信，并顯示到LCD上。下面給出串口通信USart部分程序：1.FPGA程序：Module1（協(xié)議部分）：Libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;--Uncommentthefollowinglibrarydeclarationifusing--arithmeticfunctionswithSignedorUnsignedvalues--useIEEE.NUMERIC
2、_STD.ALL;--Uncommentthefollowinglibrarydeclarationifinstantiating--anyXilinxprimitivesinthiscode.--libraryUNISIM;--useUNISIM.VComponents.all;entitytxisport(din:instd_logic_vector(7downto0);sout:outstd_logic;clk:instd_logic;len_r:outstd_Logic_vector(3downto0);txclk:instd_logic)
3、;endtx;architectureBehavioraloftxistypesis(start,shift,stop,delay1,delay2);--typesis(start1,shift1,stop1,delay1,start2,shift2,stop2,delay2,start3,shift3,stop3,delay3,start4,shift4,stop4,delay4);signalstate:s:=start;signaltxcnt_r,len:std_logic_vector(3downto0);signalsout1:std_l
4、ogic;signalthr:std_logic_vector(7downto0);signalclk1:std_logic;beginprocess(txclk)beginiftxclk='1'andtxclk'eventthenthr<=din;endif;endprocess;process(txclk)variabletsr:std_logic_vector(7downto0);variablecount:integerrange0to480:=0;variablecount1:integerrange0to4800:=0;beginift
5、xclk='1'andtxclk'eventthencasestateiswhenstart=>tsr:=thr;sout1<='0';--傳輸起始位txcnt_r<=(others=>'0');--傳輸數(shù)據(jù)位數(shù)計(jì)數(shù)清0state<=shift;whenshift=>sout1<=tsr(0);--數(shù)據(jù)位傳輸?shù)?位數(shù)據(jù)tsr(6downto0):=tsr(7downto1);--填充數(shù)據(jù)tsr(7):='0';txcnt_r<=txcnt_r+1;if(txcnt_r=7)thenstate<=stop;endif;whenstop=>sout1<
6、='1';state<=delay1;whendelay1=>ifcount<120thencount:=count+1;elsecount:=0;iflen<7thenstate<=start;len<=len+1;elsestate<=delay2;endif;endif;whendelay2=>ifcount1<2400thencount1:=count1+1;elsecount1:=0;len<="0000";state<=start;endif;endcase;sout<=sout1;len_r<=len;endif;endprocess
7、;process(clk)variablenc:integerrange0to100000000:=0;beginifclk='1'andclk'eventthenif(nc>50000000ornc<0)thennc:=0;endif;nc:=nc+1;if(nc>25000000)thenclk1<='0';elseclk1<='1';endif;endif;endprocess;--process(clk1)--begin--ifclk1='1'andclk1'eventthen--len<="000";--endif;--endproces
8、s;endBehavioral;Module2（數(shù)據(jù)發(fā)送部分）：Libraryieee;useieee.std_logic
