資源描述：
《ERP.概念原理啟動(dòng)大會(huì)》由會(huì)員上傳分享，免費(fèi)在線閱讀，更多相關(guān)內(nèi)容在教育資源-天天文庫。
1、15.5VDHL程序設(shè)計(jì)實(shí)例5.5.1常用組合電路的設(shè)計(jì)組合邏輯是電路設(shè)計(jì)的基礎(chǔ),組合邏輯的描述可通過并行信號(hào)賦值語句或純組合邏輯行為的進(jìn)程語句來實(shí)現(xiàn)。并行賦值語句：1、簡單信號(hào)賦值語句2、條件信號(hào)賦值語句3、選擇信號(hào)賦值語句進(jìn)程語句：為了保證一個(gè)進(jìn)程語句能生成組合邏輯，在進(jìn)程語句里所有被讀入的信號(hào)都必須包含在該進(jìn)程語句的敏感表中。25.5.1.1門電路1、與門方法1：直接信號(hào)賦值libraryieee;useieee.std_logic_1164.all;entityand_2isport(a:ins
2、td_logic;b:instd_logic;y:outstd_logic);endand_2;architecturebehaveofand_2isbeginy<=aandb;endbehave;3方法2：進(jìn)程內(nèi)信號(hào)賦值注意要將a和b都加入敏感信號(hào)表。architecturebehavofand_2isbeginprocess(a,b)beginy<=aandb;endprocess;endbehav;4方法3：進(jìn)程if條件賦值經(jīng)過分析發(fā)現(xiàn)，只有a和b都為1的時(shí)候y才會(huì)輸出1。所以描述如下：archi
3、tecturebehavofand_2isbeginprocess(a,b)beginif(a=‘1’andb=‘1’)theny<=‘1’;elsey<=‘0’;endif;endprocess;endbehav;5方法4：進(jìn)程if條件賦值經(jīng)過分析發(fā)現(xiàn)，a=‘1’時(shí)，y會(huì)跟蹤b的變化，即y<=b。architecturebehavofand_2isbeginprocess(a,b)beginifa=‘1’theny<=b;elsey<=‘0’;endif;endprocess;endbehav;62.
4、與非門libraryieee;useieee.std_logic_1164.all;entitynand_2isport(a:instd_logic;b:instd_logic;y:outstd_logic);endnand_2;architecturebehaveofnand_2isbeginy<=anandb;endbehave;75.5.1.2編碼器與譯碼器8線－3線編碼器8－3編碼器d0d1d2d3d4d5d6d7q0q1q2圖5.4.18－3線編碼器用case語句libraryieee;use
5、ieee.std_logic_1164.all；entitycoderisport(d:instd_logic_vector(7downto0);q:outstd_logic_vector(2downto0));endcoder;architecturertlofcoderisbeginp1:process(d)begincasediswhen"01111111"=>q<="111";when"10111111"=>q<="110";when"11011111"=>q<="101";when"11101
6、111"=>q<="100";when"11110111"=>q<="011";when"11111011"=>q<="010";when"11111101"=>q<="001";when"11111110"=>q<="000";whenothers=>q<="000";endcase;endprocessp1;endrtl;8architecturertlofcoderisbeginwithdselectq<="111"when"01111111","110"when"10111111","101"w
7、hen"11011111","100"when"11101111","011"when"11110111","010"when"11111011","001"when"11111101","000"when"11111110","000"whenothers;endrtl;用with_select語句：優(yōu)先編碼器可用when_else或if_then_else實(shí)現(xiàn)93-8譯碼器：libraryieee;useieee.std_logic_1164.all;entitydecoderisport(data
8、_in:instd_logic_vector(2downto0);g1,g2a,g2b:instd_logic;d:outstd_logic_vector(7downto0));enddecoder;architecturebehaveofdecoderisbegin用case語句:10process(data_in,g1,g2a,g2b)beginif(g1='1'andg2a='0'andg2b='0')thencasedata_ini
