EDA 技術(shù)與 VHDL 實(shí)驗(yàn)程序

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1、EDA技術(shù)與VHDL實(shí)驗(yàn)參考程序?qū)嶒?yàn)一1.用vhdl語(yǔ)言設(shè)計(jì)2選1多路選擇器。Libraryieee;Useieee.std_logic_1164.all;Entitymux21aisPort(a,b,s:inbit;Y:outbit);Endmux21a;Architectureoneofmux21aisBeginY<=awhens='0'elseb;Endarchitectureone;2.將此二選一多路選擇器看成是一個(gè)元件mux21a，利用元件例化語(yǔ)句描述圖所示雙2選1多路選擇器。Libraryieee;Useieee.std_logi

2、c_1164.all;EntitymuxkisPort(a1,a2,a3,s0,s1:instd_logic;outy:outstd_logic);Endmuxk;ArchitecturebhvofmuxkisComponentmux21aPort(a,b,s:instd_logic;Y:outstd_logic);Endcomponent;Signaltmp:std_logic;BeginU1:mux21aportmap(a=>a2,b=>a3,s=>s0,y=>tmp);U2:mux21aportmap(a=>a1,b=>tmp,s=>s

3、1,y=>outy);Endarchitecturebhv;實(shí)驗(yàn)二1.用vhdl語(yǔ)言設(shè)計(jì)D邊沿觸發(fā)器。Libraryieee;Useieee.std_logic_1164.all;Entitydff1isPort(clk,d:instd_logic;Q:outstd_logic);End;Architecturebhvofdff1isSignalq1:std_logic;BeginProcess(clk,q1)BeginIfclk'eventandclk='1'thenq1<=d;Endif;endprocess;Q<=q1;endbhv;2

4、.用vhdl語(yǔ)言設(shè)計(jì)D鎖存器。Libraryieee;Useieee.std_logic_1164.all;Entitydff2isPort(clk,d:instd_logic;Q:outstd_logic);End;Architecturebhvofdff2isBeginProcess(clk,d)beginIfclk='1'thenq<=d;endif;Endprocess;endbhv;實(shí)驗(yàn)三1.用vhdl設(shè)計(jì)含異步清零和同步時(shí)鐘使能的十進(jìn)制加法計(jì)數(shù)器。Libraryieee;Useieee.std_logic_1164.all;Use

5、ieee.std_logic_unsigned.all;Entitycnt10isPort(clk,rst,en:instd_logic;Cq:outstd_logic_vector(3downto0);Cout:outstd_logic);Endcnt10;Architecturebehavofcnt10isBeginProcess(clk,rst,en)Variablecqi:std_logic_vector(3downto0);BeginIfrst='1'thencqi:=(others=>'0');Elsifclk'eventandc

6、lk='1'thenIfen='1'thenIfcqi<9thencqi:=cqi+1;Elsecqi:=(others=>'0');endif;Endif;endif;Ifcqi=9thencout<='1';Elsecout<='0';endif;Cq<=cqi;Endprocess;endbehav;2.用vhdl設(shè)計(jì)含異步清零和同步時(shí)鐘使能的十進(jìn)制加減可控計(jì)數(shù)器。Libraryieee;Useieee.std_logic_1164.all;Useieee.std_logic_unsigned.all;Entitydcnt10isPor

7、t(clk,rst,en,s:instd_logic;Cq:outstd_logic_vector(3downto0);Cout:outstd_logic);Enddcnt10;Architecturebehavofdcnt10isBeginProcess(clk,rst,en,s)Variablecqi:std_logic_vector(3downto0);BeginIfrst='1'thencqi:=(others=>'0');Elsifclk'eventandclk='1'thenIfen='1'thenIfs='1'thenIfcqi

8、<9thencqi:=cqi+1;Elsecqi:=(others=>'0');endif;Elsifs='0'thenIfcqi>0thencqi:=cqi-1;