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1、Quartus常見錯(cuò)誤分析ErrorWarning:VHDLProcessStatementwarningatrandom.vhd(18):signalresetisinstatement,butisnotinsensitivitylist----沒把singal放到process（）中2Warning:Foundpinsingasundefinedclocksand/ormemoryenablesInfo:AssumingnodeCLKisanundefinedclock-=-----可能是說
2、設(shè)計(jì)中產(chǎn)生的觸發(fā)器沒有使能端3Error:VHDLInterfaceDeclarationerrorinclk_gen.vhd(29):interfaceobject"clk_scan"ofmodeoutcannotberead.Changeobjectmodetobufferorinout.------信號(hào)類型設(shè)置不對，out當(dāng)作buffer來定義4Error:Nodeinstance"clk_gen1"instantiatesundefinedentity"clk_gen"-------引用
3、的例化元件未定義實(shí)體－－entity"clk_gen"5Warning:Found2node(s)inclockpathswhichmaybeactingasrippleand/orgatedclocks--node(s)analyzedasbuffer(s)resultinginclockskewInfo:Detectedrippleclock"clk_gen:clk_gen1
4、clk_incr"asbufferInfo:Detectedrippleclock"clk_gen:clk_gen1
5、
6、clk_scan"asbuffer6Warning:VHDLProcessStatementwarningatledmux.vhd(15):signalorvariable"dataout"maynotbeassignedanewineverypossiblepaththroughtheProcessStatement.Signalorvariable"dataout"holdsitspreviousineverypathwithnonewassignment,whichmaycreateac
7、ombinationalloopinthecurrentdesign.7Warning:VHDLProcessStatementwarningatdivider_10.vhd(17):signal"cnt"isreadinsidetheProcessStatementbutisn'tintheProcessStatement'ssensivititylist-----缺少敏感信號(hào)8Warning:Noclocktransitionon"counter_bcd7:counter_counter_c
8、lk
9、q_sig[3]"register9Warning:Reducedregister"counter_bcd7:counter_counter_clk
10、q_sig[3]"withstuckclockporttostuckGND10Warning:Circuitmaynotoperate.Detected1non-operationalpath(s)clockedbyclock"class[1]"withclockskewlargerthandatadelay.SeeCompilationRe
11、portfordetails.11Warning:Circuitmaynotoperate.Detected1non-operationalpath(s)clockedbyclock"sign"withclockskewlargerthandatadelay.SeeCompilationReportfordetails.12Error:VHDLerroratcounter_clk.vhd(90):actualport"class"ofmode"in"cannotbeassociatedwithf
12、ormalport"class"ofmode"out"------兩者不能連接起來13Warning:Ignorednodeinvectorsourcefile.Can'tfindcorrespondingnodename"class_sig[2]"indesign.------沒有編寫testbench文件，或者沒有編輯輸入變量的值testbench里是元件申明和映射14Error:VHDLBindingIndicationerroratfreqdetect_top.vhd(19):port"
