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1、摘要現(xiàn)代科技領(lǐng)域?qū)﹄娮赢a(chǎn)品的要求越來越高微處理器如單片機DSP系統(tǒng)的穩(wěn)定性和抗干擾能力是電子工程師面臨的一大難題監(jiān)控技術(shù)就是解決這一難題的有效手段之一使用監(jiān)控IC已成為當(dāng)今的設(shè)計潮流因為它大大減少了系統(tǒng)電路的復(fù)雜性和元器件數(shù)量并可以提高系統(tǒng)可靠性和精確度現(xiàn)在的監(jiān)控IC向著多功能系統(tǒng)級發(fā)展從早期僅有的電壓監(jiān)測發(fā)展到后來看門狗數(shù)據(jù)保護電池切換等功能也歸入監(jiān)控電路廣泛應(yīng)用于計算機工業(yè)控制通信家用電器儀器儀表等領(lǐng)域本課題的目的就是設(shè)計一款多功能低成本低功耗微處理器電源監(jiān)控電路芯片它集成了基準(zhǔn)帶隙電壓源電壓比較器時基振蕩看門狗等模塊整合了掉電保護上電復(fù)位看門狗定時手動復(fù)位等多個功能能夠監(jiān)控電
2、源電壓電池故障和微處理器或微控制器的工作狀態(tài)為了降低芯片的成本和功耗采用了CMOS的制造工藝在設(shè)計中采用了傳統(tǒng)的模擬電路設(shè)計方法定制設(shè)計要求電路設(shè)計電路仿真版圖繪制這一自底向上的全定制方案使用的設(shè)計工具都是Cadence公司提供的全定制IC設(shè)計平臺Virtuoso仿真工具Spectre和驗證工具Diva本芯片設(shè)計基于上海貝嶺的1.2mCMOS2P2MC12DDR工藝線對仿真結(jié)果的分析表明本文設(shè)計的電源監(jiān)控電路芯片完全符合設(shè)計要求降低了成本提高了芯片的性能達到了設(shè)計目的關(guān)鍵詞:電源管理芯片模擬電路帶隙基準(zhǔn)電壓源CMOS比較器時基振蕩看門狗版圖設(shè)計IABSTRACTWiththeinc
3、reasingrequirementofelectronicproductsinthemodernscienceandtechnologyfield,moreandmorechallengessuchasanti-jammingandstabilityinthemicroprocessorarebroughttoelectronicengineers.Supervisorytechnologyisoneeffectivewaytosettletheseproblems.Voltagemonitoring,supervisoryintegratedcircuitsareverypop
4、ularinthedesigns,inthattheycannotonlyreducethedesigncomplexityandthenumberofcomponents,butimprovesystemreliabilityandaccuracysignificantly,comparedtoseparateICsanddiscretecomponents.ModernsupervisoryICshavethecharacteristicofmultifunction,whichallowsmanyfunctionsbesidesvoltagemonitoringsuchasw
5、atchdogtiming,dataprotectionandbatteryswitching.Foralltheseadvantages,supervisoryICshavebeenappliedinmanyfields,includingcomputers,criticalPpowermonitoringandintelligentinstruments.Inthisthesis,amultifunctional,low-cost,low-consumePsupervisorycircuitschipwasdesigned.Inthisdesign,thebandgap,vol
6、tagedifference,oscillatorandwatchdogtimermoduleswereintegratedandmanyfunctionsincludingpower-onreset,watchdogtiming,manual-resetandpower-downprotectionwererealized.Toreducetheconsumeandcost,theCMOSprocesswasadopted.Duringthedesign,wefollowedfull-customdesignmethodology:confirmthespec-circuitde
7、sign-simulation-layoutdesign-tapout.TheEDAtoolsusedinthedesignincludestheCadenceVirtuosocustomdesignplatform,thesimulationtool-Spectreandtheverificationtool-DIVA.ThedesignwasbasedontheBeilingofshanghai1.2mCMOSC12DDRprocess.Thesimulation
