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1、中北大學(xué)學(xué)位論文基于LVDS的某武器遙測(cè)系統(tǒng)數(shù)據(jù)記錄儀研制摘要信息通信產(chǎn)業(yè)日新月異,對(duì)數(shù)據(jù)的存儲(chǔ)速度、容量、功耗、可靠性等要求越來越高,這就需要一套穩(wěn)定可靠的數(shù)據(jù)存儲(chǔ)系統(tǒng)。本設(shè)計(jì)結(jié)合國內(nèi)外研究現(xiàn)狀和課題要求,設(shè)計(jì)和研發(fā)了基于LVDS的某武器遙測(cè)系統(tǒng)數(shù)據(jù)記錄儀研制。該系統(tǒng)搭建了以FPGA為基礎(chǔ)的硬件平臺(tái),通過總線型LVDS接收數(shù)字信號(hào),經(jīng)緩存后,以TTL電平形式存儲(chǔ)到大容量FLASH存儲(chǔ)器中。本設(shè)計(jì)利用FPGA開發(fā)周期短、可重構(gòu)性強(qiáng)和VHDL硬件語言的高靈活性等優(yōu)勢(shì),實(shí)現(xiàn)了系統(tǒng)工作模式的控制,完成了接口設(shè)計(jì)和時(shí)序邏輯設(shè)計(jì);采用多點(diǎn)到多點(diǎn)總線型架構(gòu)的LVDS接收器
2、來接收采編裝置的大量數(shù)據(jù),其特點(diǎn)為速度快,性能可靠性高。應(yīng)用FPGA內(nèi)部FIFO進(jìn)行數(shù)據(jù)緩存,減小了體積簡(jiǎn)化了電路設(shè)計(jì),實(shí)現(xiàn)了數(shù)據(jù)緩存和跨時(shí)鐘域的速度匹配。采用大容量閃存做存儲(chǔ)器使系統(tǒng)具有了存儲(chǔ)數(shù)據(jù)量大以及掉電數(shù)據(jù)不丟失的特點(diǎn)。同時(shí)采用光電隔離對(duì)干擾進(jìn)行了有效的控制。總體設(shè)計(jì),既節(jié)省了開發(fā)成本,又縮短了開發(fā)周期,同時(shí)具有體積小、可靠性高等特點(diǎn)。本文對(duì)LVDS高速總線傳輸技術(shù)和大容量存儲(chǔ)技術(shù)等關(guān)鍵技術(shù)在本系統(tǒng)中的應(yīng)用進(jìn)行了具體的敘述;并對(duì)系統(tǒng)總體方案設(shè)計(jì)、各功能模塊的具體實(shí)現(xiàn)原理以及設(shè)計(jì)過程中的各種問題與解決方法給出了詳細(xì)的說明和研究。用模擬信號(hào)源的方法驗(yàn)證了系
3、統(tǒng)的可實(shí)現(xiàn)性與可靠性。最終通過與實(shí)測(cè)結(jié)果的比對(duì),得出本系統(tǒng)的可行性、可靠性、有效性。關(guān)鍵詞:LVDS,F(xiàn)PGA,存儲(chǔ)測(cè)試,F(xiàn)LASH中北大學(xué)學(xué)位論文ResearchandProduceofcertainweapontelemetrysystemDataloggerBasedonLVDSAbstractTherapiddevelopmentofinformationandcommunicationindustry,moreandmorespecificationsofdatastoragedevicesarerequired,suchasstoragespeed
4、,capacity,powerconsumptionandreliability,whichrequiresareliabledatastoringsystem.thisthesiscombinesresearchstatusandrequirementsofthesubject,wedesignedaweapontelemetrysystemDataloggerbasedonLVDStocompletethedatastoringtasks.ThesystemisbuiltbasedonaFPGAhardwareplatform,whichreceivest
5、hedigitalsignalsthroughLVDSbusandaftercachestored,thedataisstoredintothelargecapacityFLASHmemoryintheformofTTLlevel.ThedesignusestheadvantagesofFPGA’sshortdevelopmentcycleandstrongreconstructingability,togetherwiththehighflexibilityofhardwaredescriptivelanguageVHDL,toachievethecontr
6、olofthesystemworkingmode,completedthedesignofinterfaceandsequentiallogicdesign.WithMultipointtomultipointbusarchitectureLVDSreceivertoreceivelargeamountsofdataeditingdevice,whichischaracterizedbyhighspeed,performanceandreliability.ApplicationofFPGAinternalFIFOdatacache,toreducethevo
7、lume,simplifiesthecircuitdesign,hasrealizedthedatacacheandclockdomaincrossingspeedmatching.Usinglargecapacityflashmemorytodosystemhasalargeamountofstoreddataandthecharacteristicsofthedataisnotlost.Atthesametimeadoptphotoelectricisolationforeffectivecontrolofinterference.Thiskindofde
8、signsavesdevelopmen