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1、3-8譯碼器的VHDL設計1.實體框圖2.程序設計正確的程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDECODER38AISPORT(A2,A1,A0,S1,S2,S3:INSTD_LOGIC;Y:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDENTITYDECODER38A;ARCHITECTUREONEOFDECODER38AISSIGNALS:STD_LOGIC_VECTOR(5DOWNTO0);BEGINS<=A2&A1&A0&S1&S2&S3
2、;WITHSSELECTY<="11111110"WHEN"000100","11111101"WHEN"001100","11111011"WHEN"010100","11110111"WHEN"011100","11101111"WHEN"100100","11011111"WHEN"101100","10111111"WHEN"110100","01111111"WHEN"111100","11111111"WHENOTHERS;ENDARCHITECTUREONE;3.仿真波形圖4.仿真波形分析當S1S2S3=10
3、0時，只有當A2A1A0=111時，Y[7]才輸出低電平，否則為高電平，當A2A1A0=110時，Y[6]才輸出低電平，否則為高電平，當A2A1A0=101時，Y[5]才輸出低電平，否則為高電平，Y[4]到Y(jié)[0]同理?？梢娫摮绦蛟O計的是3-8譯碼器三、共陽極數(shù)碼管七段顯示譯碼器的VHDL設計1.實體框圖2.程序設計正確的程序LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYDISPLAY_DECODERISPORT(A3,A2,A1,A0:INSTD_LOGIC;Y:OUTSTD_
4、LOGIC_VECTOR(6DOWNTO0));ENDENTITYDISPLAY_DECODER;ARCHITECTUREONEOFDISPLAY_DECODERISSIGNALS:STD_LOGIC_VECTOR(3DOWNTO0);BEGINS<=A3&A2&A1&A0;WITHSSELECTY<="1111110"WHEN"0000","0110000"WHEN"0001","1101101"WHEN"0010","1111001"WHEN"0011","0110011"WHEN"0100","1011011"WHE
5、N"0101","1011111"WHEN"0110","1110000"WHEN"0111","1111111"WHEN"1000","1111011"WHEN"1001","0000000"WHENOTHERS;ENDARCHITECTUREONE;3.仿真波形圖4.仿真波形分析由圖可知，當A3A2A1A0=0000時，輸出Y[6]到Y(jié)[0]對應為1111110，即只有g不亮，數(shù)碼管顯示為0，A3A2A1A0=0001時，輸出對應為0110000，數(shù)碼管顯示為1，A3A2A1A0=0010時，輸出對應為1101101，
6、數(shù)碼管顯示為2，其他同理，當A3A2A1A0>1001，即大于9，數(shù)碼管無顯示。由此可知，程序設計的是七段顯示譯碼管。
