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1、1、仿真中是利用modelsim軟件的自帶加載仿真數(shù)據(jù)功能實(shí)現(xiàn)的仿真。所以沒有編仿真數(shù)據(jù)文件。數(shù)據(jù)流依次是（47）01000111001100110110011011001100。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYframeISPORT(clk:INSTD_LOGIC;data:INSTD_LOGIC_vector(0to7);syna:OUTSTD_LOGIC);ENDframe;ARCHITECTUREbehaviorOFframeISTYPEstateIS(s0,
2、s1,s2,s3,s4);SIGNALs,next_s:state;記錄狀態(tài)SIGNALd:STD_LOGIC_vector(0to7);描述數(shù)據(jù)流SIGNALnum:INTEGERRANGE0TO15;num用來找到禎頭計(jì)數(shù)禎長的SIGNALevenorodd:STD_LOGIC;記錄是否找到禎SIGNALadd:INTEGERRANGE0TO2;記錄出錯(cuò)次數(shù)BEGINPROCESS(clk,data)逐字節(jié)找禎頭BEGINIF(next_s/=s0)andrising_edge(clk)THENIFnum=15THENn
3、um<=0;ELSEnum<=num+1;ENDIF;d<=data;ELSIFrising_edge(clk)THENd<=data;ENDIF;ENDPROCESS;PROCESS(next_s)狀態(tài)轉(zhuǎn)換BEGINs<=next_s;ENDPROCESS;process(clk)進(jìn)入狀態(tài)機(jī)BEGINIFclk'eventANDclk='1'THENCASEsISWHENs0=>IFd="01000111"THENnext_s<=s1;syna<='0';evenorodd<='1';ELSEnext_s<=s0;syna
4、<='0';evenorodd<='0';ENDIF;WHENs1=>syna<='0';IFnum=15THENIFd="01000111"THENnext_s<=s2;evenorodd<='1';ELSEnext_s<=s0;syna<='0';evenorodd<='0';ENDIF;ENDIF;WHENs2=>IFnum=15THEN找到三禎，準(zhǔn)備進(jìn)入s3同步態(tài)IFd="01000111"THENnext_s<=s3;syna<='0';evenorodd<='1';ELSEnext_s<=s0;syna<='0'
5、;evenorodd<='0';ENDIF;ENDIF;WHENs3=>syna<='1';IFnum=15THENIFd="01000111"THENnext_s<=s4;evenorodd<='1';add<=0;ELSEifadd=2then如果發(fā)現(xiàn)第三禎仍舊next_s<=s0;出錯(cuò)，回到s0初態(tài)syna<='0';evenorodd<='0';elseadd<=add+1;next_s<=s4;syna<='1';evenorodd<='0';endif;endif;endif;WHENs4=>IFnum=15TH
6、ENIFd="01000111"THENnext_s<=s3;syna<='1';evenorodd<='1';add<=0;ELSEifadd<=1thennext_s<=s0;syna<='0';evenorodd<='0';elseadd<=add+1;next_s<=s4;syna<='1';evenorodd<='0';endif;endif;endif;ENDCASE;ENDIF;ENDPROCESS;ENDARCHITECTURE;基于FPGA的數(shù)字系統(tǒng)設(shè)計(jì)_課程設(shè)計(jì)(題目附后)1、程序?qū)崿F(xiàn)了在ts_in輸入‘
7、47’‘1F’‘FF’時(shí)將din的值加入tsout的目的（見源碼后仿真結(jié)果圖）。結(jié)果正確。1、其中din的輸入值需要另外設(shè)置buffer中給予緩沖，在空禎到來時(shí)按照先入先出的原則輸入到ts_out中，但因時(shí)間，和資料有限，試過多次總會(huì)出些其他錯(cuò)誤，未能實(shí)現(xiàn)。因此僅將din輸入的值在空禎到來時(shí)填入tsout的空位。LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYadd_stringISPORT(ts_out:OUTstd_logic_vector(7downto0));ENDadd_s
8、tring;ARCHITECTUREadd_inOFadd_stringISsignalsyna,reset:STD_LOGIC;signalts_in,din:std_logic_vector(7downto0);SIGNALclk:STD_LOGIC:='1';SIGNALadd:ST
