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1、VHDL數(shù)字鐘設(shè)計(jì)報(bào)告一.數(shù)字鐘總體設(shè)計(jì)方案：1.1設(shè)計(jì)目的①正確顯示時(shí)、分、秒；②可手動(dòng)校時(shí)，能分別進(jìn)行時(shí)、分的校正；③整點(diǎn)報(bào)時(shí)功能；1.2設(shè)計(jì)思路數(shù)字鐘的設(shè)計(jì)模塊包括：分頻器、去抖動(dòng)電路、校時(shí)電路、“時(shí)、分、秒”計(jì)數(shù)器、校時(shí)閃爍電路、整點(diǎn)報(bào)時(shí)和譯碼顯示電路。每一個(gè)功能模塊作為一個(gè)實(shí)體單獨(dú)進(jìn)行設(shè)計(jì)，最后再用VHDL的例化語句將各個(gè)模塊進(jìn)行整合，生成頂層實(shí)體top。該數(shù)字鐘可以實(shí)現(xiàn)3個(gè)功能：計(jì)時(shí)功能、設(shè)置時(shí)間功能和報(bào)時(shí)功能。二．?dāng)?shù)字鐘模塊細(xì)節(jié)2.1分頻器（fenpin）本系統(tǒng)共需3種頻率時(shí)鐘信號(hào)（1024Hz、512Hz、
2、1Hz）。為減少輸入引腳，本系統(tǒng)采用分頻模塊，只需由外部提供1024Hz基準(zhǔn)時(shí)鐘信號(hào)，其余三種頻率時(shí)鐘信號(hào)由分頻模塊得到。分頻原理：為以1024Hz基準(zhǔn)時(shí)鐘經(jīng)1024分頻得到512Hz,1Hz頻率時(shí)鐘信號(hào)。分頻器管腳代碼：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;entityfenpinisport(clk1024:instd_logic;clk1,clk512:outs
3、td_logic);endfenpin;architecturecmloffenpinisbeginprocess(clk1024)variablecount1:integerrange0to512;variableq1:std_logic;beginifclk1024'eventandclk1024='1'thenifcount1=512thenq1:=notq1;count1:=0;elsecount1:=count1+1;endif;endif;clk1<=q1;endprocess;process(clk1024)
4、variablecount512:integerrange0to1;variableq512:std_logic;beginifclk1024'eventandclk1024='1'thenifcount512=1thenq512:=notq512;count512:=0;elsecount512:=count512+1;endif;endif;clk512<=q512;endprocess;endcml;2．2校時(shí)電路（jiaoshi）本模塊要實(shí)現(xiàn)的功能是：正常計(jì)時(shí)、校時(shí)、校分在每個(gè)狀態(tài)下都會(huì)產(chǎn)生不同控制信號(hào)實(shí)現(xiàn)相應(yīng)的功
5、能。校時(shí)管腳圖代碼：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityjiaoshiisport(rst,rvs,select_rvs,mtime,mclkin,hclkin:instd_logic;hclkout,mclkout:outstd_logic);endjiaoshi;architecturecmlofjiaoshiissignalh_m:std_logic;beginp1:process(rst,rvs,hc
6、lkin,mclkin,h_m,mtime)beginifrst='0'thennull;elsifrvs='1'thenhclkout<=hclkin;mclkout<=mCLKin;elsifh_m='0'thenhclkout<=hclkin;mclkout<=mtime;elsehclkout<=mtime;mclkout<=mclkin;endif;endprocess;p2:process(select_rvs)beginifselect_rvs'eventandselect_rvs='1'thenh_m<=n
7、oth_m;endif;endprocess;endcml;管腳圖仿真圖2.3時(shí)計(jì)數(shù)器（hour）分計(jì)數(shù)器(mine)秒計(jì)數(shù)器(second)時(shí)計(jì)數(shù)器管腳圖時(shí)代碼：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityhourisport(rst,hclk:instd_logic;hour0,hour1:bufferstd_logic_vector(3downto0));endhour;architecturecmlofhou
8、risbeginprocess(rst,hclk,hour0,hour1)beginifrst='0'thenhour0<="0000";hour1<="0000";elsifhclk'eventandhclk='1'thenifhour0="0011"andhour1="0010"thenhour0<
