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1、SFTW230:SystemsandNetworksIComputerOrganizationTopicscovered:Chapter5.TheMemorySystem(I)Dr.WUWen,FST,UMOutline?Somebasicconcepts?Memoryhierarchy?Cachememories?SemiconductorRAMmemories15.1Somebasicconcepts?Maximumsizeofthememorydependsontheaddressingscheme:?16-bitcomputer
2、generates16-bitaddressesandcanaddressupto216=66536=64Kmemorylocations.?32-bitcomputergenerates32-bitaddressesandcanaddressupto232=4Gmemorylocations.210–1K=220–1M=–1G=230–1T=240?Mostmachinesbyteaddressablebutretrieve/storedatainwordsaboutonememoryaccess.2Somebasicconcepts
3、(cont.)ProcessorMemoryk-bitaddressbusMARn-bitdatabuskUpto2addressableMDRlocationsWordlength=nbitsControllines(,MFC,etc.)R/W?RecallthatthedatatransfersbetweenaprocessorandmemoryinvolvestworegistersMARandMDR.?MAR:kbitslong;MDR:nbitslong.?memoryunitbeupto2k.?Controllinesinc
4、ludeR/WandMemoryFunctionCompleted(MFC)?coordinatingdatatransfers.3Memoryhierarchy(5.4and5.5inTextbook)?Thememorystructureofacomputer?Multiplelevelsofmemorieswithdifferentspeedsandsizes.?Closertoprocessor,fasterandsmaller4MemoryhierarchyProcessor?ProcessorregistersFastest
5、accessistothedataheldinRegistersregistersareatthetopofthememoryhierarchy.IncreasingIncreasingIncreasingsizespeedcostperbit?ProcessorcachePrimaryL1Relativelysmallamountofmemorythatcachecanbeimplementedontheprocessorchip.?Twolevelsofcache.Level1(L1)cacheSecondaryisonthepro
6、cessorchip.Level2(L2)cacheL2cacheisinbetweenmainmemoryandprocessor.(earlierprocessorgeneration)?MainmemoryMainMuchlarger,butmuchslowerthancachememorymemory.?Magneticdisks.Hugeamountofinexpensivestorage.Magneticdisksecondarymemory5CacheMemories?Cachememory?Anarchitectural
7、arrangementwhichmakesthemainmemoryappearfastertotheprocessorthanitreallyis.?Toreducetheexecutiontime?WeshouldimprovethepossibilityoffindingthecurrentexecutedinstructionsinthecacheHowTo??AnalysistheprogramexecutionpatternDuringsomeperiodoftime,manyinstructionsinlocalizeda
8、reasofaprogramareexecutedmoreoftenthanothers.localityofreference6Localityofreference?Twoforms:?Temporal
