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《串行數(shù)據(jù)轉(zhuǎn)并行數(shù)據(jù)與并行數(shù)據(jù)轉(zhuǎn)串行數(shù)據(jù).doc》由會員上傳分享，免費在線閱讀，更多相關(guān)內(nèi)容在教育資源-天天文庫。
1、并行轉(zhuǎn)串行代碼moduleparallel_to_serial(clk,data_in,data_out,state);inputclk;input[7:0]data_in;outputdata_out;output[7:0]state;reg[7:0]state=0;regdata_out;parameterstate1=0;parameterstate2=1;parameterstate3=2;parameterstate4=3;parameterstate5=4;parameterstate6=5;parameters
2、tate7=6;parameterstate8=7;always@(posedge?clk)//并行輸入,串行輸出begin?case(state)state1:begindata_out<=data_in[0];state<=state2;end??state2:begindata_out<=data_in[1];state<=state3;end??state3:begindata_out<=data_in[2];state<=state4;end??state4:begindata_out<=data_in[3];st
3、ate<=state5;end??state5:begindata_out<=data_in[4];state<=state6;end??state6:begindata_out<=data_in[5];state<=state7;end??state7:begindata_out<=data_in[6];state<=state8;end??state8:begindata_out<=data_in[7];state<=state1;end????default:state<=state1;?endcaseendendmo
4、dule串行到并行moduleserial_to_parallel(nreset,clk,en,in,out,count,data);input??nreset,clk,en,in;output[3:0]out;output[3:0]data;output[1:0]count;reg[1:0]count;//移位計數(shù)，控制并行數(shù)據(jù)更新，這里是4bit并行數(shù)據(jù)reg[3:0]data;reg[3:0]out;always@(posedge?clkornegedgenreset)?????begin??????????if(~n
5、reset)???????????????count<=2'b00;??????????elseif(en)???????????????count<=count+2'b01;?????end//移位always@(posedge?clkornegedgenreset)?????begin??????????if(~nreset)???????????????data<=4'b0000;??????????elseif(en)???????????????data<={data[2:0],in};?????end//并行輸出
6、always@(posedge?clkornegedgenreset)?????begin??????????if(~nreset)???????????????out<=4'b0000;??????????elseif(en&&(count==2'b00))???????????????out<=data;?????endendmodule
