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集成電路分析與設計第1講認識集成電路設計及其設計過程2023/4/241
《集成電路分析與設計》課程主要介紹什么內容?CMOS數(shù)字集成電路(CMOSdigitalIC)IC的發(fā)展歷史及現(xiàn)狀(HistoryofIC)IC設計流程和方法(DesignprocessandMethodology)IC制造工藝技術(Fabricationprocess)ICEDA（CAD）工具使用(EDAtools)CMOS反相器設計(CMOSInverter)CMOS組合邏輯門設計(CombinationalLogicCircuit)CMOS時序邏輯電路設計(SequentialLogicCircuit)IC版圖設計(Layout)IC仿真技術(Simulation)存儲器電路設計介紹(MemoryCircuits)模擬IC設計介紹(AnalogIC)2023/4/242
《集成電路分析與設計》課程信息課程性質：是一門專業(yè)基礎課程主要介紹CMOS數(shù)字集成電路設計的基礎知識共40課時（32理論課時+8實驗課時）完成4個實驗對準備從事IC行業(yè)的學生來講，本課程只是一個基礎，還需要繼續(xù)深入學習更多關于IC設計的知識，如數(shù)字IC深入，模擬IC，RFIC等。2023/4/243
實驗內容（共8學時）實驗一（2學時）反相器電路設計（SimulationandLayout）實驗二（2學時）NAND電路設計（SimulationandLayout）實驗三（2學時）AND電路設計（SimulationandLayout）實驗四（2學時）D觸發(fā)器電路設計（SimulationandLayout）2023/4/244
Project（選作內容）完成一個4?4SRAM芯片的設計3人一組項目過程：A期中OralpresentationB期末OralpresentationC項目報告書一份D3人項目成績相同2023/4/245
GradingPolicy課堂提問和作業(yè)10%實驗20%考試（開卷）70%規(guī)則：（1）1個問題和4次作業(yè)，每次/個2分，共10分；（2）每個實驗完成得5分，共20分；（3）點名1次不到，10分沒了；（4）抄作業(yè)，抄實驗報告，相應分數(shù)沒了；（5）請假規(guī)則：必須有正規(guī)請假手續(xù)和課前請假。2023/4/246
本課程推薦書目教材中文版周潤德等譯，數(shù)字集成電路設計透視第二版，電子工業(yè)出版社(JanM.Rabaey,etal.DigitalIntegratedCircuits,2nde,PrenticeHall,2004)參考書Sung-Mo(Steve)Kang,YusufLeblebici,CMOSDigitalIntegratedCircuitsAnalysis&Design,3rdEdition,McGraw-Hill2003R.JacobBaker,CMOSCircuitDesign,Layout,andsimulation,3rdEdition,Wiley,2010韓雁，集成電路設計CAD/EDA工具實用教程，機械工業(yè)出版社，20102023/4/247
IC設計優(yōu)秀書目推薦模擬集成電路Razavi，模擬CMOS集成電路設計，清華大學出版社，2005通用參考書（Bible）威斯特，CMOS超大規(guī)模集成電路設計，第三版，中國電力出版社2023/4/248
幾個常見縮略詞CMOS(complementarymetaloxidesemiconductor)IC(integratedcircuit)VLSI(verylargescaleintegrated)ULSI(ultra-largescaleintegrated)MOSFET(metaloxidesemiconductorfieldeffecttransistors)SPICE(simulationprogramwithintegratedcircuitemphasis)2023/4/249
認識集成電路和集成電路設計為什么需要集成電路？與以前的集成電路設計相比，為什么現(xiàn)在的集成電路設計出現(xiàn)了不同以及現(xiàn)在的集成電路設計遇到了哪些新的挑戰(zhàn)？未來，集成電路將如何發(fā)展？2023/4/2410
為什么需要集成電路?Integrationreducesdevicesize（減小尺寸）Laptop,iPod,mp3,cellphone,...Integrationimprovesthedesign（提高性能）higherspeed;lowerpowerconsuption;morereliable.Integrationreducesmanufacturingcost（降低成本）BOM(BoardofMaterials)costreducesMassICproductionreducescost2023/4/2411
ElectronicsIndustryDesign,fab,applicationEducationSoftwareCommunication/NetworkingFabcost:$2-$3billionDrivingforceofworldeconomyLargeinvestment:fab,packaging,design,EDAPentium?4“Northwood”55Mtransistors/2-2.5GHzL=0.13μm2023/4/2412
Moore’sLaw(1965)GordonMoore–IntelFounder“Thenumberoftransistorsonachipdoubledevery18to24months.”Electronics,April19,1965.GordonMooreIntelCo-FounderandChairmainEmeritusImagesource:IntelCorporationwww.intel.com2023/4/2413
InformationRevolutionElectronicsystemincars.Electronicfinancialsystem:e-banking,e-money,e-stock,RFIDlablePersonalcomputing/entertainmentMedicalelectronicsystems.Internet:routers,firewalls,servers,storagesElectroniclibrary(Google,...)DVDR/W,HDTV,InteractiveTVIngeneral,consumerelectronicsetc...2023/4/2414
ChallengesofICDesignComplexity:Multi-milliontransistorsonasinglechip(smallersize/fasterspeed)Multipleandconflictingspecificationsforhighperformance(power/speed/throughput)Competition:ShortdesigntimeDesignTools:Multipletoolsinvolved,ComplexdesignflowAnalogBasebandDigitalBaseband(DSP+MCU)PowerManagementSmallSignalRFPowerRF2023/4/2415
RelatedtoICJobs?Layoutdesigners?Circuitdesigners(Digital/Analog/RF)?Architects?Test/Verificationengineers?Fabricationengineers?Systemdesigners(SoC)?CADtoolprogrammersEmbeddedSystemdevelopersSoftwareprogrammers2023/4/2416
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TheTransistorRevolutionFirsttransistorBellLabs,1947J.Bardeen,W.Shockley,andW.Brattain(1956NobelprizeLaureate)2023/4/2418
1958年J.Kilby（TI）研制成功第一個集成電路1959年R.Noyce（Fairchild）第一個利用平面工藝制成集成電路TheFirstIntegratedCircuits2023/4/2419
TheFirstIntegratedCircuitsBipolarlogic1960’sECL3-inputGateMotorola1966FirstcommercialIClogicgates–Fairchild1960TTL–1962intothe1990’sECL–1974intothe1980’s2023/4/2420
Intel4004Micro-Processor19702300transistors~1MHzoperation2023/4/2421
IntelPentium(IV)microprocessorPentium?4“Northwood”CommercialProduction:Year2001L=0.13μm6MLCuLow-kFC-PGA22023/4/2422
MOSFETTechnologyMOSFETtransistor-Lilienfeld(Canada)in1925andHeil(England)in1935CMOS–1960’s,butplaguedwithmanufacturingproblems(usedinwatchesduetotheirpowerlimitations)PMOSin1960’s(calculators)NMOSin1970’s(4004,8080)–forspeedCMOSin1980’s–preferredMOSFETtechnologybecauseofpowerbenefitsBiCMOS,Gallium-Arsenide,Silicon-GermaniumSOI,Copper-LowK,strainedsilicon,High-kgateoxide...2023/4/2423
WorldwideSemiconductorRevenueSource:ISSCC2003G.Moore“Noexponentialisforever,but‘forever’canbedelayed”2023/4/2424
1’’Waferin1964vs.300mm(12”)Waferin20032023/4/2425
IBMPowerPC970(130nm)20031.8Ghz58M118mm2ApplePowerG5,thefastestPCin2003,hasdualPPC970CPU2023/4/2426
TwochipsyouareseeingtodayMicroprocessorASIC(ApplicationSpecificIC)2023/4/2427
State-of-theArt:LeadMicroprocessors2023/4/2428
State-of-theArt:LeadMicroprocessors(uptodate)Pentium4180nm(2001)1.7GHz42Mtransistors217mm2Pentium4130nm(2003)3.2GHz55MTransistors131mm2Pentium490nm(2004)3.4Hz125MTransistors112mm2Pentiumon65nm(2005/2006)250Million Pentiumon45nm(2007)400to500MillionFreq(HZ)TransistorsDiesizemm2PowerDateServerIBMPower4+1.7G180M267N/A2003Itanium21.5G410M374130W2003IBMPower52G276M389N/A2004/2PCIBMPowerPC9701.8G58M11842W2003/6Pentium43.2G55M13182W2003/6AMDAthlon642.2G105M19289W2003/9Pentium4(Prescott)3.4G125M112103W2004/2(Alluse0.13umtechnologyexceptPentium4–Prescott,whichuses90nmtech)2023/4/2429
State-of-theArt:LeadMicroprocessors(uptodate)300mmwaferandPentium4IC.PhotoscourtesyofIntel.2023/4/2430
WhatADigitalDesignerNeedstoKnow...“MicroscopicProblems”?Ultra-highspeeddesignInterconnect?Noise,Crosstalk?Reliability,Manufacturability?PowerDissipation?Clockdistribution.“MacroscopicIssues”?Time-to-Market?MillionsofGates?High-LevelAbstractions?Reuse&IPAvailability?systemsonachip(SoC)?Predictability?etc.2023/4/2431
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>95%2023/4/2439
如何設計一個集成電路？2023/4/2440
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TheVLSIdesignprocess工程的藝術Maybepartoflargerproductdesign.Majorlevelsofabstraction:specificationarchitecturelogicdesigncircuitdesignlayoutdesign2023/4/2442
MajorSegmentsofICIndustryFablessDesignHousesEDAToolsCompaniesDesignServiceCompaniesLibrary&IPProvidersDedicatedICManufacturers(Foundry)Post:EDA:ElectronicDesignAutomationIP:siliconIntellectualPropertyIDM:IntegratedDeviceManufacturerIntegratedservicePackaging&TestingHouses2023/4/2443
ASICDesignStylesFullCustomDesignFlowCircuitiscreatedbycomposingatransistornetlistSPICEsimulationisperformedtoverifythecircuitKnownas“capture-and-simulate”paradigmLayoutismostlydonemanuallyPopularforhigh-performancemicroprocessors&memoriesCell-BasedSynthesisFlowDesignisfirstdescribedbyHardwareDescriptionLanguage(e.g.,VerilogandVHDL)Basedonacelllibrary,netlistiscreatedbysynthesistoolsKnownas“describe-and-synthesize”paradigmLayoutcanbedonethroughautomatictools2023/4/2444
DetailedCustomDesignFlowBlockSpecification(FiniteStateMachine,ArithmeticExpression,BooleanExpression)LogicDesignGate-LevelNetlistTransistorNetlistTechnologyMappingSPICESimulationSPICEModelLayoutDesignLayoutLayoutRulesDesignRuleChecking(DRC)Layoutvs.SchematicCheck(LVS)Parasitic(orwiring)RCextractionPost-LayoutSPICESimulationCheckifSPECismet?Ifyes,done.Otherwise,gobacktooptimizethedesign2023/4/2445
ASimpleExampleFunctionalityOne-bitbinaryfull-adderTechnology1mmn-wellCMOStechnologySpeedInputtooutputdelay<5nsArea<3000mm2PowerDissipation<1mWat5voltsand200MHzFull-adderABSumCarry_outSum=A⊕B⊕C=ABC+ABC+ABC+ACBCarry_out=AB+BC+CA(majorityfunction)BooleanDescriptionC2023/4/2446
LogicDesignLogicminimizationtrick:Thecarry_outsignalisusedtorealizethefunctionofsignalsuminordertoreducetheoverallcircuitsize.Today’slogicsynthesistools(suchasDesignCompiler)incorporatingsomeadvancedalgorithms,isabletoperformautomaticlogicminimization.x=Carry_out#of‘1’sInA,B,CCarry_outSum012300110101(A+B+C)x=>exactlyoneofA,B,Cis‘1’2023/4/2447
Transistor-LevelSchematicTechnologymappingManysimpleANDORgatesaremergedintoacomplexgate(oracellinthecelllibrary)TransistoraspectratiopMOS(W/L)isusuallylargerthannMOS(W/L),e.g.,2:1xyxyx=(AB+BC+CA)y=(A+B+C)x+ABC)2023/4/2448
InitialLayoutPost-layoutSPICEsimulationincludesthe“parasiticresistance&capacitance”ismoreaccuratethanthepre-layoutsimulation(pre-sim)Ratioofchannelwidths2:12023/4/2449
I/OSimulationWaveformsPropagationtimetPHLortPLHasdefinedaboveLow-to-highpropagationtime（傳播延時）tPLH=8.2ns!Gottogobacktooptimizethedesign!!!C(Carry_in)Sum2023/4/2450
OptimizedLayoutTransistorSizingchangestheaspectratios(W/L)ofselectedtransistorsAlargeraspectratiomayleadtoahigherspeedWireSizingisalsomorerecentlyproposedPropagationDelay<5ns!2023/4/2451
FullCustomDesignExample（another)A/DPLAI/OcompRAMMetal1ViaMetal2I/OPadRandomlogic(standardcelldesign)2023/4/2452
Cell-BasedDesignFlowArchitecturedesignSystem-levelintegrationlayoutNoviolationMemorymoduleFunctionalmodelTestbenchRTLcoding&simulationRTLcodeCellLibrarysynthesisviewRTL-synthesis(DesignCompiler)NetlistphysicalviewPlace&Route(Apollo)LayoutviolationPost-LayoutTimingCheck(DesignTime)SDFSDF:standarddelayformat2023/4/2453
DesignStyles StandardCell(CellBased)EachcellhasequalheightICservicecompanyprovidescelllibrary(forspecificfab.com.):500~1200cellsDesignrule+AbuttingruleCell1Cell2Space/2DCCBACCDCDBBCCCCellMetal1Metal2FeedthroughGNDVDDCDABCelllibrary2023/4/2454
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集成電路將如何發(fā)展？未來的25年內，CMOS技術仍將保持其主流技術地位；SystemonChip(SOC),系統(tǒng)芯片是發(fā)展趨勢。2023/4/2456
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Foundry——國內2023/4/2464
Foundry——臺灣地區(qū)和境外2023/4/2465
國內設計企業(yè)炬力集成電路設計有限公司中星微電子有限公司上海杰得微電子有限公司大唐微電子技術有限公司圣邦微電子有限公司瑞芯微電子有限公司展訊通信（上海）有限公司安凱技術有限公司上海海爾集成電路有限公司北京華虹集成電路設計有限責任公司硅谷數(shù)模半導體有限公司中國華大集成電路設計集團有限公司2023/4/2466
國內設計企業(yè)華潤矽威科技（上海）有限公司深圳艾科創(chuàng)新微電子有限公司智多微電子（上海）有限公司昂寶電子(上海)有限公司晶門科技（深圳）有限公司深圳致芯微電子有限公司深圳市力合微電子有限公司重慶西南集成電路設計有限公司北京思旺電子技術有限公司杭州友旺電子有限公司華亞微電子(上海)有限公司2023/4/2467
國內設計企業(yè)蘇州華芯微電子有限公司上海富瀚微電子有限公司北京凌訊華業(yè)科技有限公司紹興芯谷科技有限公司北京中科億芯信息技術有限公司杭州士蘭微電子有限公司杭州國芯科技有限公司等等2023/4/2468
