fpga奇數(shù)和偶數(shù)分頻器和半整數(shù)及任意小數(shù)分頻器設(shè)計(jì)(verilog程序)

《fpga奇數(shù)和偶數(shù)分頻器和半整數(shù)及任意小數(shù)分頻器設(shè)計(jì)(verilog程序)》由會(huì)員上傳分享，免費(fèi)在線閱讀，更多相關(guān)內(nèi)容在行業(yè)資料-天天文庫(kù)。

1、EngineerLhraceAuthor:---EngineerLhrace1、半整數(shù)分頻占空比不為50%//說(shuō)明：設(shè)計(jì)的史上最好用的半整數(shù)分頻占空比不為50%，包含設(shè)計(jì)思路modulediv_5(clk,clk_div,cnt1,cnt2,temp1,temp2);//N+0.5inputclk;outputclk_div;outputreg[31:0]cnt1,cnt2;outputregtemp1,temp2;initialbegintemp1=0;temp2=1;end//首先進(jìn)行初始化，temp1=0;temp2=1paramet

2、erN=5;//設(shè)定分頻系數(shù)為N+0.5always@(posedgeclk)//temp1上升沿跳變beginif(cnt1==2*N)//2*Nbegincnt1[31:0]<=32'd0;endelsebegincnt1[31:0]<=cnt1[31:0]+32'd1;endif(cnt1==32'd0)begintemp1<=1;end//高電平時(shí)間為N+1;if(cnt1==N+1)begintemp1<=0;end//低電平時(shí)間為N;endalways@(negedgeclk)//temp2下降沿跳變beginif(cnt2==

3、2*N)//2*Nbegincnt2[31:0]<=32'd0;endelsebegincnt2[31:0]<=cnt2[31:0]+32'd1;endif(cnt2==32'd0)begintemp2<=0;end//低電平時(shí)間為N;if(cnt2==N)begintemp2<=1;end//高電平時(shí)間為N+1;endassignclk_div=temp1&&temp2;//邏輯與endmodule//如果要進(jìn)行N+0.5分頻//思路：總的來(lái)說(shuō)要進(jìn)行N+1+N=2N+1次分頻//在時(shí)鐘的上升沿和下降沿都進(jìn)行跳變//上升沿進(jìn)行占空比為N+1

4、比N的時(shí)鐘temp1;//下降沿進(jìn)行占空比為N比N+1的時(shí)鐘temp2;//最后div=temp1&&temp2即可得到所需要的半整數(shù)分頻分頻5.5仿真結(jié)果EngineerLhrace2、奇數(shù)分頻占空比為50%//說(shuō)明：奇數(shù)分頻。modulediv_5(clk,clk_div,cnt1,cnt2,temp1,temp2);//inputclk;outputclk_div;outputreg[31:0]cnt1,cnt2;outputregtemp1,temp2;parameterN=5;//設(shè)定分頻系數(shù)always@(posedgeclk)

5、beginif(cnt1==N-1)//N-1進(jìn)行N計(jì)數(shù)begincnt1[31:0]<=32'd0;endelsebegincnt1[31:0]<=cnt1[31:0]+32'd1;endif(cnt1==32'd0)begintemp1<=1;end//if(cnt1==(N-1)/2)begintemp1<=0;end//當(dāng)計(jì)數(shù)到(N-1)/2時(shí)翻轉(zhuǎn)endalways@(negedgeclk)beginif(cnt2==N-1)//N-1begincnt2[31:0]<=32'd0;endelsebegincnt2[31:0]<=cn

6、t2[31:0]+32'd1;endif(cnt2==32'd0)begintemp2<=1;end//;if(cnt2==(N-1)/2)begintemp2<=0;end//當(dāng)計(jì)數(shù)到(N-1)/2時(shí)翻轉(zhuǎn);endassignclk_div=temp1

7、

8、temp2;//邏輯或endmoduleEngineerLhrace2任意小數(shù)分頻Modulexiao_fenpin(clk,divclk);//占空比為50%任意小數(shù)分頻inputclk;regclkout;regdelete;parameterk=10;reg[k-1:0]p;para

9、meterM=13;//clk輸入的頻率，parameterN=11;//需要得到的頻率//假如是13Mhz,要生成一個(gè)11M的頻率//占空比為50%//由M時(shí)鐘分頻等到N頻率的方法。always@(posedgeclk)beginif(p>=M)beginp[k-1:0]<=p[k-1:0]-M+N;delete<=1'b0;endif(p

10、inif(delete==1)clkout<=1;elseclkout<=clk;endregcnb;wirecnc;outputdivclk;EngineerLhraceass