奇數(shù)分頻器(verilog)

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1、奇數(shù)分頻器??/***********************************************************?????????Filename??????:??????odd_divider.v?????????Author?????????:??????Cardinal?????????Company?????:??????Cardinal?????????Revision??????:??????2010/03/1517:20?????????Description???:??????Ex

2、erciseofaodddivider?????????描述??????????:??????這是一個奇數(shù)分頻器???????????????????????????????奇數(shù)分頻法有多種實(shí)現(xiàn)方式，這里采用的是???????????????????????????????錯位相“或”法.這里實(shí)現(xiàn)的實(shí)現(xiàn)的是3分頻???????????????????????????????占空比是50%，類似可以實(shí)現(xiàn)任意的N次奇數(shù)????????????????????????????????分頻*******************

3、***************************************/moduleODD_DIVIDER(???clk_in,???rst_n,???clk_out???);????????????parameter?????????width=2;????????????input???????????????clk_in;??????input???????????????rst_n;??????output????????????clk_out;????????????reg??????[width-1

4、:0]??????cnt_posedge,cnt_negedge;??????reg???????????????????????????clk_1toN_p,clk_1toN_n;????????????always@(posedgeclk_in)??????//上升沿分頻，占空比1:2?????????begin????????????if(!rst_n)???????????????begin??????????????????cnt_posedge<=0;??????????????????clk_1toN_p

5、<=0;???????????????end????????????else???if(cnt_posedge==2'b10)???????????????????????????cnt_posedge<=0;?????????????????????else???????????????????????????begin??????????????????????????????cnt_posedge<=cnt_posedge+1;??????????????????????????????clk_1toN_p<=~

6、clk_1toN_p;????????????????????????????????????????????????????????????end?????????end???????????????always@(negedgeclk_in)??????//下升沿分頻，占空比1:2?????????begin????????????if(!rst_n)???????????????begin??????????????????cnt_negedge<=0;??????????????????clk_1toN_n<=

7、0;???????????????end????????????else???if(cnt_negedge==2'b10)???????????????????????????cnt_negedge<=0;?????????????????????else???????????????????????????begin??????????????????????????????cnt_negedge<=cnt_posedge+1;??????????????????????????????clk_1toN_n<=~cl

8、k_1toN_n;????????????????????????????????????????????????????????????end?????????end???????????????assignclk_out=clk_1toN_n

9、

10、clk_1toN_p;?//錯位相或?????????????????????en