verilog分頻器代碼

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1、verilog分頻器代碼//偶數(shù)倍分頻：偶數(shù)倍分頻應(yīng)該是大家都比較熟悉的分頻，通過計(jì)數(shù)器計(jì)數(shù)是完全可以實(shí)現(xiàn)的。//如進(jìn)行N倍偶數(shù)分頻，那么可以通過由待分頻的時(shí)鐘觸發(fā)計(jì)數(shù)器計(jì)數(shù)，當(dāng)計(jì)數(shù)器從0計(jì)數(shù)到N/2-1時(shí)，輸出時(shí)鐘進(jìn)行翻轉(zhuǎn)，//并給計(jì)數(shù)器一個(gè)復(fù)位信號，使得下一個(gè)時(shí)鐘從零開始計(jì)數(shù)。以此循環(huán)下去。這種方法可以實(shí)現(xiàn)任意的偶數(shù)分頻。moduleodd_division(clk,rst,count,clk_odd);?input???????clk,rst;?output??????clk_odd;?output[3:0]?count;?reg?????????clk_odd;?reg[3:0]?

2、???count;?parameter???N=6;????always@(posedgeclk)?????if(!rst)???????begin?????????count<=1'b0;?????????clk_odd<=1'b0;???????end?????else?????????????if(count

3、????????clk_odd<=~clk_odd;??????????????endendmodule?//奇數(shù)倍分頻：//歸類為一般的方法為：對于實(shí)現(xiàn)占空比為50%的N倍奇數(shù)分頻，首先進(jìn)行上升沿觸發(fā)進(jìn)行模N計(jì)數(shù)，計(jì)數(shù)從零開始，//到（N－1）/2進(jìn)行輸出時(shí)鐘翻轉(zhuǎn)，然后經(jīng)過（N-1）/2再次進(jìn)行翻轉(zhuǎn)得到一個(gè)占空比非50%奇數(shù)n分頻時(shí)鐘。//再者同時(shí)進(jìn)行下降沿觸發(fā)的模N計(jì)數(shù)，到和上升沿過（N-1）/2時(shí)，輸出時(shí)鐘再次翻轉(zhuǎn)生成占空比非50%的奇數(shù)n分頻時(shí)鐘。//兩個(gè)占空比非50%的n分頻時(shí)鐘相或運(yùn)算，得到占空比為50%的奇數(shù)n分頻時(shí)鐘。moduleeven_division(clk,rst,

4、count1,count2,clk_even);?input???????clk,rst;?output[3:0]?count1,count2;?output??????clk_even;?reg[3:0]????count1,count2;?reg?????????clkA,clkB;?wire????????clk_even;?parameter???N=5;????assignclk_re??=~clk;???assignclk_even=clkA

5、clkB;??????always@(posedgeclk)?????if(!rst)????????begin?????????cou

6、nt1<=1'b0;?????????clkA?<=1'b0;?????????????????end?????else???????if(count1<(N-1))?????????begin???????????count1<=count1+1'b1;???????????????????????if(count1==(N-1)/2)?????????????begin???????????????clkA<=~clkA;?????????????end????????????????????????end????????????????else?????????begin??????

7、?????clkA<=~clkA;???????????count1<=1'b0;?????????end????????????????????always@(posedgeclk_re)???if(!rst)?????begin???????count2<=1'b0;???????clkB?<=1'b0;?????end???else?????if(count2<(N-1))???????begin?????????count2<=count2+1'b1;???????????????????????if(count2==(N-1)/2)?????????????begin??????

8、?????????clkB<=~clkB;?????????????end??????????????????????end??????????????else???????begin?????????clkB<=~clkB;?????????count2<=1'b0;???????end??????????endmodule